Three wire, 3D core memories provide an excellent combination of low cost and high speed and have therefore become very popular in recent years. In such memories X and Y drive wires are passed through the cores in orthogonal rows and columns. Each carries a half select current so that a core at an intersection of a selected X or row wire and a selected Y or column wire receives two half select currents for full selection. A different crossover is provided for each bit position of a memory. Thus, an 18 bit memory must have 18 crossovers for each combination of an X wire and a Y wire so that 18 cores are fully selected simultaneously.
A pair of sense-inhibit conductors is provided for each bit position and is inductively coupled to every core in the bit position, usually running parallel to the Y wires. Consequently, during a read cycle the separate sense-inhibit conductor pairs can separately sense core switching signals for each bit position. Similarly, during a write cycle half select current can be passed through any desired sense-inhibit conductor pairs in a direction opposite to the Y write current to cancel the Y write current at desired bit positions and prevent the switching of cores thereat. Those cores thus remain in the zero state while selected cores in bit positions which do not receive a partially cancelling inhibit current are switched to the one state.
Because the inhibit current driver circuitry must be duplicated at each bit position (i.e. 18 bit positions require 18 inhibit driver circuits) it is desirable to minimize the total cost and power consumption of such circuits in a memory. One technique which has been used to reduce cost is to utilize two parallel sense-inhibit conductors at each bit position, each inductively coupling half of the cores. Because core switching signal losses and time delays along a sense-inhibit conductor make sensing difficult and are largely determined by the length of a conductor and the number of cores thereon, there is a practical limit to the number of cores coupled by a single conductor. By using two sense-inhibit conductors in parallel at each bit position, the number of cores at each bit position can be doubled so that only half as many inhibit driver circuits are required. This reduction in the number of circuits helps to compensate for the use of more complex and more expensive electronics required for three wire systems compared to four wire systems with separate sense wires and inhibit wires.
However, the use of two sense-inhibit conductors doubles the current to be supplied by each inhibit current driver. At the same time, fast memory operation requires rapid rise of inhibit current to a reasonably well regulated steady state magnitude. The large number of inhibit current drivers and the requirement for double currents make the inhibit drivers one of the most energy demanding systems in a core memory. An inhibit current driver must therefore meet stringent operating requirements at minimum cost and power consumption.
Memory cores present a highly inductive load to a sense-inhibit conductor. Consequently, in order to decrease inhibit current rise time and thereby improve total cycle time it is common to drive a sense-inhibit conductor with an initial voltage that is greater than the voltage required to maintain steady state operation. The simplest way is to use a large series resistor driven from a high voltage source. Initially there is no current flow and the total voltage is applied across the core inductance. Eventually the resistor limits the steady state current. While simple and inexpensive, this arrangement results in large power losses in the resistor. Other arrangements involve switching between high and low voltage but require additional timing and control circuitry which increase the cost.